3/6/12MHz 5-stage pipeline X3-32bit microprocessor.
MIP-I, II instruction set.
128 KB on-chip flash programming memory.
2k x 32-bit data cache (SRAM).
2k x32-bit boot ROM.
1 cycle interrupt response with atomic control.
6 external interrupt pads.
Up to 16 internal interrupts.
One 20-bit general purpose timer for 4 channel PWM output.
Two 20-bit general purpose timer for 1 channel PWM output.
8-bit basic timer with 8-bit pre-scaler.
Window and independent watchdog timer.
16-bit sigma-delta ADC with adjustable sample clock frequency.
12-bit v2p module.
Support 8 multiplexed input channels or 4 differential input pairs.
Two UART/LIN.
SPI interface up to 3 Mbit/s.
6/12/24/48MHz 5-stage pipeline X3-32bit microprocessor.
MIP-I, II instruction set.
32-128 KB on-chip flash programming memory.
2k x 32-bit data cache (SRAM).
2k x32-bit boot ROM.
1 cycle interrupt response with atomic control.
2 external interrupt pads.
Up to 16 internal interrupts.
Three 16-bit general purpose timer for 2 channel PWM outputs.
Two 20-bit general purpose timer for 1 channel PWM output.
Window and independent watchdog timer.
12-bit SAR-ADC with adjustable sample clock frequency.
Support 8 multiplexed input channels.
4 Op-amp modules.
3 comparator modules.
32 GP IOs.
Three UART/LIN.
SPI interface up to 32 Mbit/s.